UWEE Tech Report Series

Decipher: Architecture Development of Reconfigurable Encryption Hardware


Kenneth Eguro, Scott Hauck

Domain-specific, FPGA, encryption, AES


Domain-specific FPGAs attempt to improve performance over general- purpose reconfigurable logic by providing only the necessary flexibility needed for a range of applications. One typical optimization is the replacement of more universal fine-grain logic elements with a specialized set of coarse-grain functional units. While this improves computation speed and reduces routing complexity, this also introduces a unique problem. It is not clear how to simultaneously consider all applications in a domain and determine the most appropriate overall number and ratio of different functional units. In this paper we use the candidate algorithms of the Advanced Encryption Standard competition to explore this problem. We introduce three algorithms that attempt to balance the hardware needs of the domain and optimize the overall performance and area requirements for an encryption-specialized reconfigurable array.

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