UWEETR-2004-0006 Author(s): Keywords: Abstract Contrary to prevailing consumer conceptions of efficient silicon use, previous research efforts have shown that designing routing- poor FPGAs may yield significant area gains. In this paper we show that conventional wirelength-centric placement tools are unable to deal with the challenges that routing-limited CAD problems present. We believe that this problem is present given today's architectures and will become more important as devices scale. |